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SY89858U
Precision Low Power 1:8 LVPECL Fanout Buffer with Internal Termination
General Description
The SY89858U is a 2.5V/3.3V precision, highspeed, fully differential LVPECL 1:8 fanout buffer optimized to provide eight identical output copies with less than 30ps of skew and less than 10pspp total jitter. It can process clock signals as fast as 2.0GHz. The differential input includes Micrel's unique, 3-pin input termination architecture that allows the SY89858U to directly interface to LVPECL, CML, and LVDS differential signals (AC- or DC-coupled) as small as 100mV without any level shifting or termination resistor networks in the signal path. The result is a clean, stub-free, low-jitter interface solution. The LVPECL (100k temperature compensated) outputs feature 800mV typical swing into 50 loads, and provide fast rise/fall times guaranteed to be less than 200ps. The SY89858U operates from a 2.5V 5% supply or 3.3V 10% supply and is guaranteed over the full industrial temperature range of -40C to +85C. For applications that require a higher speed fanout buffer, consider the SY58032U. The SY89858U is (R) part of Micrel's high-speed, Precision Edge product line. All support documentation can be found on Micrel's web site at: www.micrel.com.
Precision Edge
(R)
Features
* Precision 1:8, LVPECL fanout buffer * Low power: 238mW (2.5V) * Guaranteed AC performance over temperature and supply voltage: - Wide operating frequency: DC to 2.0GHz - <380ps In-to-Out tpd - <200ps tr/tf - <30ps skew * Ultra-low jitter design: - <1psRMS random jitter - <1psRMS cycle-to-cycle jitter - <10psPPtotal jitter * 100k LVPECL compatible outputs * Fully differential inputs/outputs * Accepts an input signal as low as 100mV (200mVpp) * Unique patent pending input termination and VT pin accepts DC-coupled and AC-coupled differential inputs (LVPECL, LVDS, and CML) * Power supply 2.5V 5% or 3.3V 10% * -40C to +85C industrial temperature range (R) * Available in 32-pin (5mm x 5mm) MLF package
Applications
* * * * All SONET and GigE clock distribution All Fibre Channel clock and data distribution Network routing engine timing distribution High-end, low-skew multiprocessor synchronous clock distribution
Markets
* * * *
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarksof Amkor Technology. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
LAN/WAN Enterprise servers ATE Test and measurement
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SY89858U
Typical Application
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SY89858U
Ordering Information(1)
Part Number SY89858UMG SY89858UMGTR
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals Only. 2. Tape and Reel.
(2)
Package Type MLF-32 MLF-32
Operating Range Industrial Industrial
Package Marking SY89858 with Pb-Free bar-line indicator SY89858 with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
32-Pin MLF (MLF-32)
(R)
Pin Description
Pin Number 3, 6 Pin Name IN, /IN Pin Function Differential Input: This differential input accepts AC- or DC-coupled signals as small as 100mV (200mVPP). Each pin of this pair internally terminates to a VT pin through 50W. Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap: Each side of the differential input pair terminates to this VT pin. The VT pin provides a center-tap to a termination network for maximum interface flexibility. See the "Input Interface Applications" section for more details. Reference Voltage: This output biases to VCC-1.2V (typical). It is used for ACcoupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01uF low ESR capacitor to VCC. Maximum sink/source capability is 1.5mA. Positive Power Supply: Bypass with 0.1mF//0.01mF low ESR capacitors as close to the VCC pins as possible. 100k LVPECL Differential Outputs: Differential buffered output copy of the input signal. The LVPECL output swing is typically 800mV into 50 to VCC-2V. Unused output pairs may be left floating with no impact on jitter. See "LVPECL Output" section. Ground: Ground pins and exposed pad must be connected to the same ground plane.
4
VT
5
VREF-AC
1, 8, 9, 16, 18, 23, 25, 32 31, 30, 29, 28, 27, 26, 22, 21, 20, 19, 15, 14, 13, 12, 11, 10 2, 7, 17, 24
VCC Q0, /Q0, Q1, /Q1, Q2, /Q2, Q3, /Q3, Q4, /Q4, Q5, /Q5, Q6, /Q6, Q7, /Q7 GND Exposed Pad
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SY89858U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................ -0.5V to +4.0V Input Voltage (VIN) ....................................-0.5V to VCC Termination Current Source or sink current on VT .................... 100mA (3) Reference Current Source or sink current on VREF-AC .............. 1.5mA LVPECL Output Current (IOUT) Continuous .................................................... 50mA Surge ........................................................... 100mA Lead Temperature (soldering, 20 sec.)............ +260C Storage Temperature (Ts) ...................-65C to 150C
Operating Ratings(2)
Supply Voltage (VCC) ....................+2.375V to +2.625V ........................................................ +3.0V to +3.6V Ambient Temperature (TA) .................. -40C to +85C (4) Package Thermal Resistance (R) MLF (JA) Still-Air ........................................................ 35C/W (R) MLF (JB) Junction-to-Board ...................................... 20C/W
DC Electrical Characteristics(5)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RIN RDIFF_IN VIH VIL VIN VDIFF_IN VT_IN VREF-AC
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Due to the limited drive capability use for input of the same package only. 4. Package Thermal Resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still air, unless otherwise stated. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Power Supply Power Supply Current Input Resistance (IN-to-VT) Differential Input Resistance (IN-to-/IN) Input High Voltage (IN, /IN) Input Low Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing |IN-/IN| IN-to-VT (IN, /IN) Output Reference Voltage
Condition
Min 2.375 3.0
Typ 2.5 3.3 95
Max 2.625 3.6 150 55 110 VCC VIH-0.1 1.7
Units V V mA V V V V
No load, max. VCC 45 90 VCC -1.2 0 See Figure 1a. See Figure 1b. 0.1 0.2
50 100
1.28 VCC-1.3V VCC-1.2V VCC-1.1V
V V
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SY89858U
LVPECL Outputs DC Electrical Characteristics(7)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C; RL = 50 to VCC -2V, unless otherwise stated.
Symbol VOH VOL VOUT VDIFF-OUT
Note: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Output HIGH Voltage Q, /Q Output LOW Voltage Q, /Q Output Voltage Swing Q, /Q Differential Output Voltage Swing Q, /Q
Condition
Min VCC-1.145 VCC-1.945
Typ
Max VCC-0.895 VCC-1.695
Units V V mV mV
See Figure 1a. See Figure 1b.
500 1000
800 1600
AC Electrical Characteristics(8)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, RL = 50 to VCC -2V, unless otherwise stated.
Symbol fMAX tPD Tpd Tempco Tskew Parameter Maximum Operating Frequency Propagation Delay (IN-to-Q) Differential Propagation Delay Temperature Coefficient Output-to-Output Skew Part-to-Part Skew Random Jitter (RJ) tJitter Deterministic Jitter (DJ) Cycle-to-Cycle Jitter Total Jitter tR, tF
Notes: 8. 9. High-frequency AC-parameters are guaranteed by design and characterization. Output-to-output skew is measured between outputs under identical conditions.
Condition VOUT 400mV
Min 2.0 180
Typ 3.0 260 115
Max 380
Units GHz ps fs/ C
o
Note 9 Note 10 Note 11 Note 12 Note 13 Note 14 At full output swing. 75 130
30 150 1 10 1 10 200
ps psRMS psPP psPP psPP ps
Output Rise/Fall Time (20% to 80%)
10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs. Part-to-part skew includes variation in tpd. 11. Random jitter is measured with a K28.7 character pattern, measured at 2.5Gbps. 12. Deterministic Jitter is measured at 2.5Gbps, with both K28.5 and 2 - 1 PRBS pattern. 13. Cycle-to-cycle jitter definition: The variation of periods between adjacent cycles, Tn - Tn-1 where T is the time between rising edges of the output signal. 14. Total jitter definition: With an ideal clock input of frequency 12 23
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SY89858U
Typical Operating Characteristics
Functional Characteristics
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SY89858U
Singled-Ended and Differential Swings
Figure 1a. Single-Ended Voltage Swing
Figure 1b. Differential Voltage Swing
Timing Diagram
Input and Output Stages
Figure 2a. Simplified Differential Input Stage
Figure 2b. Simplified LVPECL Output Stage
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SY89858U
Input Interface Applications
Option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3c. CML Interface (DC-Coupled)
Figure 3d. CML Interface (AC-Coupled)
Figure 3e. LVDS Interface (DC-Coupled)
Figure 3f. LVDS Interface (AC-Coupled)
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SY89858U
LVPECL Output Interface Applications
LVPECL has high input impedance, and very low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50 and 100 controlled impedance transmission lines. There are several techniques for terminating the LVPECL output: Parallel
Termination-Thevenin Equivalent, Parallel Termination (3-resistor), and AC-coupled Termination. Unused output pairs may be left floating. However, single-ended outputs must be terminated, or balanced.
Figure 4a. Parallel Termination-Thevenin Equivalent
Figure 4b. Parallel Termination (3-Resistor)
Related Product and Support Documentation
Part Number SY58032U Function Ultra-Precision 1:8 LVPECL Fanout Buffer w/Internal Termination MLF Application Note HBW Solutions New Products and Applications
(R)
Datasheet Link www.micrel.com/product-info/products/sy58032u.shtml www.amkor.com/products/notes_papers/MLFAppNote.pdf www.micrel.com/product-info/products/solutions.shtml
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SY89858U
Package Information
32-Pin (5mm x 5mm) MicroLeadFrame
Package Notes: 1. 2. 3. Package meets Level 2 Moisture Sensitivity Classification. All parts are dry-packaged before shipment.
(R)
Exposed pad must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2004 Micrel, Incorporated.
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